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back to article ARM busts out server-to-superphone superchips

ARM has rolled out a new series of processors – the Cortex-A50 Series – that it says will find their way into everything from smartphones to mega-data centers. The beefier member of the two-chip series has already found at least one data-center home in future ARM-based Opteron server chips, as announced this Monday by AMD. The …

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Anonymous Coward

Whose cuisine will reign supreme?

We really need an eccentric Japanese character to preside over the competition... I don't think "Chairman Kaga" is busy.

Will the plucky, underdog cooks from ARM triumph over Iron Chef Intel in Data Center stadium? Will x86 servers in 5 to 10 years be like the expensive (yet highly capable) midrange servers of today? Whose cuisine will reign supreme? Allez, cuisine!

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Anonymous Coward

Bother

I'm going to have to put off my S3 purchase...

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Anonymous Coward

Re: Bother

It's old hat now anyway. Can't possibly have a 6 month old phone if you're an Android fan. You've lost about half of it's support period.

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Terminator

Nice article

"Both the A57 and A53 employ the 64-bit extensions to the ARMv7 architecture that were announced when the 64-bit ARMv8 architecture was unveiled last October at that year's ARM TechCon."

ARMv8 is not an extension to ARMv7 by any means. It is in fact an entirely different instruction set architecture (ISA) that is not at all compatible with the previous generation. This is very different from, say, x86_64 or PPC64 that are extensions to their predecessor ISAs.

"The A57 is essentially a Cortex-A15 with the addition of the ability to handle 64-bit processing,"

Yes, except not really. Some parts are similar, but looking at the new ISA, ARMv8 is actually quite a bit more RISC-y than ARMv7-A, doesn't use predicated instructions, omits complicated multiple load/stores, and is in general better designed for parallelization and reordering by a modern CPU. Its pipeline would be quite a bit different than an A15 with its relatively complex ARM and variable length Thumb instructions. It's far more likely that the A57 is a 64-bit processor with backwards support for V7-A.

"Expect A7/A15 mashups using big.LITTLE to appear in products next year, they say."

It's nice to see that hardware designers still don't understand how software actually works. While there may in fact be chips that sport fully coherent A15+A7 complexes, the number of products that actually use them as ARM imagines will be countable on zero hands. Ask Nvidia about the Tegra 3 and its companion core for details on why this doesn't work in the real world.

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Anonymous Coward

Re: Nice article

Ask Nvidia about the Tegra 3 and its companion core for details on why this doesn't work in the real world.

I was wondering if there were any potential parallels to be learned between the Tegra's 5th core and the big.LITTLE architectures. Any recommendations on where I can read more?

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Re: Nice article

The reading here is to be done between the lines, unless you have access to internal Nvidia documents. The facts we have are thus:

1) Nvidia touts new architecture with a fast quad core and an additional low power core for live migration (effectively the same big.LITTLE architecture ARM is proposing). It will require changes to the Linux (and presumably Windows) kernels to support asymmetric scheduling and core transition for their android customers.

2) No Linux scheduler changes ever arrive from Nvidia or anyone else to support this.

3) Nvidia's repurposes the extra core as a touch detection device, a job for which it is far too powerful.

The conclusions here are either that the chip is actually broken and cannot be made to work as intended (very likely given that it is Nvidia), or that they failed to create software that does this to any benefit. My money is on both, but you'll notice that they are not trying this again for their future chips, which means that it's not just a hardware failure.

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Anonymous Coward

Re: Nice article

"ARMv8 is not an extension to ARMv7 by any means. It is in fact an entirely different instruction set architecture (ISA) that is not at all compatible with the previous generation."

This is not true. The v8 architecture supports 32 bit ARM and Thumb instructions as per v7, but adds a new 64 bit ISA to run alongside.

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Linux

Re: Nice article

@joe_bruin

"2) No Linux scheduler changes ever arrive from Nvidia or anyone else to support this."

Thats what Linaro is there for, I suppose. And also recent initiatives (e.g. proposals and commits to consolidate various vendor submissions) and other commits to the upstream have been encouraging. So the march is in right direction. As for nVidia, well they have a bitter.SWEET relations with the Linux community :)

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Anonymous Coward

Re: Nice article

From what I recall of the discussions around the launch, the 5th core was intended as the standby processor and, maybe, not even to be active at the same time as the 4 primary because the two core types were not capable of running at the same rates. I thought the switching was controlled by the chip, not ths OS.

I'm not sure big.LITTLE will have that same problem. If the two core types can run at the same rates, and the OS can't even tell if it's running on one vs. the other... switching big.LITTLE cores around shouldn't be any different than switching homogeneous cores.

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Re: Nice article

@but it runs,

Was Nvidia just too early that it's happening now from multiple vendors or do you think something else went wrong?

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Anonymous Coward

Looking at those energy usage charts, tell me again why anyone would want to use Intel shit in a phone?

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big.LITTLE

As far as I recall, the hardware on big.LITTLE processors can do the transition from low-power to high-power processors and vice-versa without intervention from the OS. Essentially, the processor state is saved in local memory and read by the other processor. That makes the situation different from Tegra3, where you have to write software to explicitly exploit the 5th core.

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Bronze badge

added crypto capabilities

Any link to a doc that describes what these new capabilities are? I'd dearly love to see a CPU that could do arithmetic over GF(2) fields, as used in AES, among other schemes. It doesn't even take much to do this in silicon, though I guess chip designers probably think it's too specialised to bother. There's always FPGA, though, I suppose...

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