To clarify

The higher the clock frequency, the more it has to wait when it cache misses. Because the difference between memory speed and CPU speed is so wide. Ideally, you want a low clock speed to minimize cache waits. And it keeps the power consumption down also. An 3GHz x86 idles ca 50% under full load. It must be worse for a 5GHz CPU, maybe it idles 70% of the time? The higher the frequency, the worse it gets because RAM speeds doesnt catch up.

And according to laws of physics, the power consumption for a CPU is proportional to

Volt x Frequency x Frequency.

This means that the single most important factor to keep power consumption down is to decrease the frequence. If you have 5GHz on a massively large CPU such as Power6, maybe it uses 400-500Watt? IBM has never released numbers on this, they keep shut. While SUN releases numbers on power consumption:

http://blogs.sun.com/bmseer/entry/sun_s_2008_summary_of

IBM brags about their Mainframes, but keep quiet on the fact that you can emulate a 30MIPS mainframe on your laptop with the emulator called "Herkules". And IBM never releases benchmarks on their mainframe cpus, why not? If they are really good, why keep quiet?

I remember when IBM bragged about their Power6 CPU stating it has 200GB/sec bandwidth or so. But upon closer scrutiny, IBM had added the bandwidth of L1 cache + L2 cache + other bandwidths in the entire chip. You can not do that. If their is one bottleneck on 5GB/sec, then the chip's entire bandwidth will not be greater than 5GB/sec. It will never reach 200GB/sec. You can not add all bandwidth in a chip. That is just plain wrong. Maybe IBM didnt knew that.