The revenue model is simple: Only the instruction set is open, not the hardware implementation to process the instruction set.
The Risc-V instruction set is maintained by a foundation based in Switzerland and details what instructions can be sent to the processor and then the output from the processor for that instruction. So, if you tell the processor to "Load memory location XXX into memory register Y", the processor does that. It doesn't specify how to do it. And, if 2 different companies develop a processor using completely different circuit designs, but both processes the input and output the same, then the software developed for that architecture will be software compatible.
One of the more important parts of the Risc-V architecture is that it does allow for additional ancillary processors and extensions that can be vendor specific. Hence, SiFive's coprocessors mentioned here.
But, SiFive designs Risc-V hardware and ancillary processors for tailored solutions. They are selling hardware. They don't have to publish their processor extension or give anything away.
Now, there are open-sourced processor circuits that anyone could pull down and then send to a fabrication facility, but those are not really optimized for anything and are very rudimentary in nature.
Risc-V is attractive as ARM and Intel will charge for even access to read their instruction sets and you have to license the rights to even use those instruction sets.